1. Field of the Invention
This invention relates generally to semiconductor memory devices, and more particularly, to data output buffer control circuits for extended data output mode.
2. Description of the Related Art
In a semiconductor memory device, the extended data output (EDO) mode of operation is different from a fast page mode of operation in that the data output signal DOUT continues to maintain the previous data without being switched to a high impedance state between data bits. Instead, to reduce the cycle time and increase speed, the data output signal DOUT is changed directly to the data of the next cycle when the column address strobe signal CASB is activated, even if the column address strobe signal CASB is set to logic "HIGH", that is, even if it is precharged.
However, in the EDO mode of operation, if a column address CAi is received during a specific column address setup time tASC, the data output buffer can malfunction. This malfunction occurs in a boosting circuit which includes a boost capacitor that is precharged and discharged at both ends. The boost capacitor plays an important role in increasing the efficiency of the boosting circuit, and therefore, such boosting circuits are widely used.
FIG. 1 is a detailed circuit diagram of a conventional data output buffer having such a boosting circuit. First and second input controllers 100 and 200 consist of transmission gates 101 and 102 and control data signals from data buses (hereinafter, referred to as nodes) DB and DBB, respectively, responsive to a data output buffer activation signal PCD. First and second latch circuits 300 and 400 include inverters 104 and 105 and inverters 106 and 107, respectively. The first and second latch circuits 300 and 400 temporarily store signals received through the transmission gates 101 and 102 and generate latch signals through nodes DBD and DBDB, respectively. NAND gates 108, 109, 111 and 112 receive the latch signals generated through the nodes DBD and DBDB and generate NAND outputs responsive to a control signal PRTSTID.
A capacitor 128, which has an input terminal connected to the output terminal of the NAND gate 108, pumps an input signal. A diode-connected NMOS transistor 117 precharges a node N3 to an external power voltage VCC. Serially connected NMOS transistors 119 and 120 supply a constant voltage to a pull-up transistor 124 which is part of a boosting driver 500. An NMOS transistor 118 has a source connected to the node N3, a gate connected to a node N2 and a drain connected to the external power voltage VCC.
If node N2 is logic "HIGH", the NMOS transistor 118 supplies the external power voltage VCC to node N3. NMOS transistors 121 and 122, each of which has one terminal connected to the external power voltage VCC and the another terminal connected to the node N2, precharge the node N2 to an internal power voltage. The nodes N1 and N2 are both terminals of a boosting capacitor 116. The data output driver 500 includes the PMOS transistor 124 and an NMOS transistor 125 which are serially connected to each other. The gate of PMOS transistor 124 is connected to the output terminal of the NAND gate 109, and the gate of the NMOS transistor 125 is connected to the output terminal of the NAND gate 111. The data output driver 500 generates a data output signal DOKP at a boosted level. An inverter 115 has an input terminal connected to the output terminal of the NAND gate 112 and generates a low voltage level data output signal DOKN.
In operation, node N1 is charged or discharged by inverter 114 which is a driver. Node N2 should be precharged to the internal power voltage for effective boosting. When node N2 is precharged, node N2 is raised to 2 VCC by boosting action if node N1 is switched from logic "LOW" to logic "HIGH". A voltage of this boosting level is supplied to the PMOS transistor 124 to drive the data output driver 500, which in turn drives the data output signal DOKP at a logic "HIGH" level out of the device.
In contrast, if node N1 is discharged to logic "LOW" by the inverter 114 of the driver, node N2 is lowered to VCC from 2 VCC. When node N1 is not fully discharged, then when node N1 is re-charged by the inverter 114 the voltage swing at node N1 is reduced and the boosting efficiency is lowered. Then, the voltage level at node N2 does not reach 2 VCC, and the voltage level of the data output signal DOKP, which is transferred through the PMOS transistor 124, is lowered, thereby lowering the voltage level of the signal output from the device. Since the output signal does not satisfy the specification value for a logic "HIGH" signal, the circuit may malfunction. The malfunction occurs when the data output signal DOKP is supposed to be at the logic "HIGH" level, but does not satisfy the specification value for a logic "HIGH" signal during the specific column address setup time in EDO mode.
FIG. 2 is an timing chart illustrating the operation of the circuit of FIG. 1. In FIG. 2, the interval P1 indicates a range in which the data output DOUT is changed to logic "HIGH" from logic "LOW". Interval P2 designates a range in which the data output is changed from logic "HIGH" to logic "HIGH" of another level by the input of another column address. Interval P3 designates a range in which the output voltage level of a logic "HIGH" signal falls even further when the current and previous data are both logic "HIGH".
Referring to FIG. 2, a column address setup time tASC designates the setup time of a column address. The data output buffer activation signal PCD in EDO mode is a signal for activating the data output buffer. Data having a logic "HIGH" level is latched in the first latch circuit 300, and data having a logic "LOW" level is latched in the second latch circuit 400. If the column address strobe signal CASB is precharged to logic "HIGH", a new column address CAi is received and a precharge voltage is generated on the data bus DB by this column address. Thereafter, if the column address strobe signal CASB is activated, and thus, the data output buffer activation signal PCD is activated, a short glitch is generated at the node DBD of the first latch circuit 300. The electric charge on the node N1 is not sufficiently discharged by this short glitch. Although the data output should be logic "HIGH" by the next address, the data output, which is supposed to be generated as a logic "HIGH" signal, has a lower level than the voltage level of the previous logic "HIGH" signal because the node N1, which is not full discharged, is again charged by the control of the address. Therefore, the data output having a lower level logic "HIGH" causes a malfunction when driving data out of the memory device since the data output is not at a sufficient level to be detected as a logic "HIGH".
Moreover, the short glitch at the node DBD appears only in EDO mode. This is because, in the EDO mode, the previous data output is maintained even if the column address strobe signal CASB is precharged, and the next data output is generated when the column address strobe signal CASB is activated again. The malfunction occurs only during the specific column address setup time.
FIG. 3 illustrates a conventional data output buffer control circuit. A first sensing circuit 10 senses and amplifies data through a bit line generated from a memory cell. A second sensing circuit 20 having input terminals connected to the output terminals of the first sensing circuit 10 senses and amplifies the data again and generates data through a driver. The data generated from the second sensing circuit 20 is applied to a first switching circuit consisting of transmission gates 100-1 and 200-1. The first switching circuit is controlled by a control signal FDBS and an inverter 103-1. The output of the first switching circuit is applied to first and second latch circuits 300-1 and 400-1. Signals latched through the first and second latch circuits 300-1 and 400-1 are applied to inverters 1141 and 115-1, respectively, which function as drivers.
The outputs of the inverters 114-1 and 115-1 are controlled by the data output buffer activation signal PCD through transmission gates 601 and 603. The outputs of the transmission gates 601 and 603 are supplied through the nodes DBD and DBDB to a data output buffer 500-1. The data output signal DOUT, which is buffered by the data output buffer 500-1, is transmitted to the exterior of the chip. In operation, the control signal FDBS, which controls the first switching circuit, is activated by the column address strobe signal CASB. If the column address strobe signal CASB is precharged, a new column address is received. The control signal is precharged to logic "HIGH" by an address transition sensing signal ATSB which is changed by the column address. Hence, although the nodes DB and DBB are not precharged, if the signal PCD is activated when ineffective data is received as logic "LOW", a short glitch is generated.
FIG. 4 illustrates another conventional data output buffer control circuit. The circuit of FIG. 4 is similar to that of FIG. 3, but includes no second switching circuit. In the circuit of FIG. 4, the control signal FDBS, which controls the first switching circuit, is activated by the column address and the column address strobe signal CASB. However, the short glitch is also generated in the circuit of FIG. 4.
Accordingly, a need remains for a data output buffer control circuit which overcomes the problems described above.